AMD unveiled the Instinct MI455X at its Advancing AI 2026 event in San Francisco, its flagship AI accelerator built on the new CDNA 5 architecture using TSMC's 2nm and 3nm process nodes. The chip packs 320 billion transistors across eight Accelerator Complex Dies, delivering up to 40.26 PFLOPS of MXFP4 compute and 20.13 PFLOPS at MXFP8 precision, alongside 432GB of HBM4 memory at up to 23.3 TB/s bandwidth — a 50% memory capacity increase over the prior MI350 generation and roughly 2.25x the memory of Nvidia's B200.
The chip is designed to operate inside AMD's new Helios rack-scale system, which combines 72 MI455X GPUs with 72 sixth-generation EPYC "Venice" CPUs to deliver 2.9 exaFLOPS of FP4 compute, 31TB of aggregate HBM4 memory, and 1.7 PB/s of memory bandwidth at the rack level. Networking runs on UALink over Ethernet, an open-consortium interconnect AMD says enables single-hop all-to-all communication across the entire rack, positioning openness as a core differentiator against Nvidia's proprietary NVLink ecosystem. Cloud partner TensorWave has already committed to deploying Helios systems at scale.
AMD is positioning the MI455X directly against Nvidia's next-generation Vera Rubin platform, which offers comparable FP8 compute but with less memory capacity per chip. A sovereign AI variant, the MI430X paired with Venice-X CPUs, targets nations and organizations that need to keep AI workloads within their borders, expected to ship in early 2027 alongside 288 teraflops of native FP64 compute for high-performance computing workloads.
